View MB86941_3673654.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds07-05602-5e fujitsu semiconductor data sheet microprocessor sparclite cmos peripheral lsi for sparclite MB86941/942 n description MB86941 and mb86942 are dedicated peripheral lsis for sparclite*. the MB86941 and mb86942 are designed to enable compact configuration of high-performance systems with sparclite architecture, and provide the following features. * : sparc is a registered trademark of sparc international base on technology developed by sun microsystems, inc. sparclite is a trademark of sparc international, inc. licensed exclusively to fujitsu microelectronics, inc. n features direct connection to sparclite register read/write in 2 clock cycles up to 30mhz. register read/write in 3 clock cycles at 40mhz (MB86941) or 50mhz (mb86942). built-in on-chip modules: ? interrupt controller interrupt input: 15 channels each interrupt input has independent masking and trigger mode settings ? 16-bit timer: 4 channels two of the four channels have prescalers each channel has five independent mode operations mode0 : periodical-interrupt mode1 : timeout-interrupt mode2 : square wave generator (continued) n package 144-pin plastic qfp (fpt-144p-m03)
2 MB86941/942 (continued) mode3: programmable one shot (software trigger) mode4: programmable one shot (external trigger) ? sdtr (serial data transmitter receiver): 2 channels mb89251a type ? timing control, cs expansion generates read, write and data strobe signals according to the requirements of external devices. ? sio (synchronous serial input/output) simple synchronous type serial input/output ? i/o port, 16-bit individual direction control by bit 5v single power supply (MB86941), 3.3v single power supply (mb86942) upward pin compatibility with mb86940c
3 MB86941/942 n pin assignment * : only for MB86941. open for mb86942. sirxd sitxd siirq n.c. wsel siclk n.c. n.c. v ss reset# clock as# rd/wr# cs# n.c. d8 d9 v dd v ss d10 d11 rs4 rs3 rs2 rs5 rs1 rs0 d12 d13 v ss d14 d15 irq15 irq14 irq13 irq12 v dd irq11 irq10 irq9 irq8 irq7 irl3 irl2 v ss irl1 irl0 irq6 irq5 irq4 irq3 cs0# ready2#* v dd v ss ready1# cs1# irq2 irq1 cs2# cs3# dsr0# cts0# rts0# trndt0 v ss dtr0# sybrk0 trdy0 rclk0 re# we# n.c. ipd15 ipd14 ipd13 ipd12 ipd11 v ss d7 d6 ipd10 ipd9 n.c. ipd8 ipd7 ipd6 d5 d4 v ss v dd d3 d2 ipd5 ipd4 ipd3 ipd2 d1 d0 v ss out3 out2 ipd1 in2 clk2 in3 clk3 v dd ipd0 clk1 in1 ack1 prsck1 out1 v ss out0 prsck0 ack0 in0 clk0 dsr1# cts1# rts1# trndt1 dtr1# v ss v dd sybrk1 trdy1 rclk1 rcvdt1 rdyout# tclk1# ds# temp1 v ss rrdy1 rrdy0 temp0 tclk0# rcvdt0 a1 a0 rcs# (top view) index (fpt-144p-m03) 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
4 MB86941/942 n block diagram * : only for MB86941. open for mb86942. cs0# to cs3# re# we# ds# internal data bus irl < 3 : 0 > clock reset# as# rd/wr# cs# rs < 5 : 0 > d < 15 : 0 > ready1# ready2#* wsel rcs# a < 1 : 0 > rdyout# ipd < 15 : 0 > siclk sirxd sitxd siirq dsr0#, cts0# rts0#, dtr0# temp0, trdy0 trndt0 tclk0# rclk0, rcvdt0 sybrk0 rrdy0 dsr1#, cts1# rts1#, dtr1# temp1, trdy1 trndt1 tclk1# rclk1, rcvdt1 sybrk1 rrdy1 ? 2 biu 1 / 2 clock 1 / 1 clock bus interface unit rcstg read/write chip select timing generator ip sio sdtr0 sdtr1 i/o port serial data input output serial data transmitter receiver serial data transmitter receiver reset irc prs0 tm0 prs1 tm1 tm2 tm3 interrupt request controller prescaler prescaler timer timer timer timer internal control bus irq1 to irq15 ack0 prsck0 clk0 in0 out0 ack1 prsck1 clk1 in1 out1 clk2 in2 out2 clk3 in3 out3
5 MB86941/942 n description of block functions 1. biu (bus interface unit) this block receives mpu (sparclite) bus signals and bus controls signals (clock, as#, rd/wr#, cs#, adr6 to adr2, d<15:0>) and generates control signals for accessing MB86941/mb86942 internal resources. it also returns that ready signal to the mpu which corresponds to the access time of each of such resources. 2. irc (interrupt request controller) this block provides 15-channel interrupt input signals to transmit the interrupt level irl <3:0> for each interrupt to the sparclite. 3. tm (timer) and prs (prescaler) tm0 to tm3 are 16-bit timers serving as periodic interrupt generation timers, a watchdog timer, and an external event counter. the operating clock can be selected from among the internal clock, the clock frequency-divided by the prescaler, and the external clock. prescalers 0 and 1 are linked with timer channels 0 and 1, respectively. each of the prescalers is initialized upon loading (or reloading) of the timer initial value of the corresponding timer. 4. sdtr (serial data transmitter receiver) sdtr0 and sdtr1 are serial data transmitter/receiver modules programmable for control of transmission and reception. the programming model is the same as that for the mb89251a. 5. rcstg (read/write timing generator) this module generates read, write, and data strobe signals conforming to the required timings for external connection of other devices. the assert timing and pulse width of each signal to be generated is programmable. 6. ip (i/o port) there are 16 i/o ports. the input/output direction of each port can be set by the control register. 7. sio (serial data input output) this block is a clock-synchronous serial interface. the transfer clock signal can be set to the internally generated or externally input one. the sio outputs data to be transmitted and inputs received data in synchronization with the transfer clock signal.
6 MB86941/942 n pin description * : only for MB86941. open for mb86942. note: numerical value of a parenthesis shows numbers of pin. mpu interface (34/33) rcstg (11) ip (16) si0 (4) sdtr1 (12) irl < 3 : 0 > clock reset# as# rd/wr# cs# rs < 5 : 0 > d < 15 : 0 > ready1# ready2#* wsel rcs# a < 1 : 0 > rdyout# cs0# to cs3# re# we# ds# ipd < 15 : 0 > siclk sirxd sitxd siirq dsr1# rts1# dtr1# cts1# trndt1 temp1 trdy1 tclk1# rcvdt1 rclk1 sybrk1 rrdy1 MB86941/2 irq15 to irq1 ack0 prsck0 clk0 in0 out0 ack1 prsck1 clk1 in1 out1 clk2 in2 out2 clk3 in3 out3 dsr0# rts0# dtr0# cts0# trndt0 temp0 trdy0 tclk0# rcvdt0 rclk0 sybrk0 rrdy0 irc (15) timer & prescaler (16) sdtr0 (12) v dd : (6) v ss : (12) n.c.: (6/7)
7 MB86941/942 1. mpu interface signals (34/33) (continued) pin symbol i/o pin no. pin name description reset# i 118 reset reset input pin input an l signal to this pin to reset the chip. clock i 119 clock system clock input pin the chip contains some modules that use the clock signal from this pin (not divided), and other modules that use the clock signal divided in half. clock not divided: biu, rcstg, ip clock divided: irc, prs0, prs1, tm0 to tm3, sdtr0, sdtr1, sio as# i 120 address strobe address strobe input pin input an l signal to this pin to determine register access according to the signals input to the rs<5:0>, cs#, and rd/wr# pins. rd/wr# i 121 read/write read/write input pin input an h signal to designate a read cycle, or an l signal to designate a write cycle. cs# i 122 chip select chip select input pin rs0 i 135 register select 0 register select input pin the combination of input signals to the rs<5:0> and cs# pins determines which register is accessed. the rs5 pin has internal pull-down resistance (MB86941 only). rs1 i 134 register select 1 rs2 i 132 register select 2 rs3 i 131 register select 3 rs4 i 130 register select 4 rs5 i 133 register select 5 ready1# o 20 ready 1 data ready output pin MB86941: open drain output with 12ma l drive capability. drives an h level signal for 3ns before going to high-z state. mb86942: normal output. ready2# signal deleted. if the ready generator circuit in the mpu is used, it is not necessary to connect this pin to the mpu. ready2# o 17 ready 2 wsel i 113 wait select wait select input pin input to this pin determines the interface timing with the mpu. fix l to set register read/write access to 3 cycles, or fix h to set register read/write access to 2 cycles. this pin has internal pull-up resistance (MB86941 only).
8 MB86941/942 (continued) pin symbol i/o pin no. pin name description d0 i/o 82 data bus 0 data i/o port these pins are used to transfer register read/write data. d1 i/o 83 data bus 1 d2 i/o 88 data bus 2 d3 i/o 89 data bus 3 d4 i/o 92 data bus 4 d5 i/o 93 data bus 5 d6 i/o 100 data bus 6 d7 i/o 101 data bus 7 d8 i/o 124 data bus 8 d9 i/o 125 data bus 9 d10 i/o 128 data bus 10 d11 i/o 129 data bus 11 d12 i/o 136 data bus 12 d13 i/o 137 data bus 13 d14 i/o 139 data bus 14 d15 i/o 140 data bus 15 irl0 o 11 interrupt request level 0 interrupt request output pin these pins are used to generate interrupts to the mpu and notify the interrupt level. irl1 o 10 interrupt request level 1 irl2 o 8 interrupt request level 2 irl3 o 7 interrupt request level 3
9 MB86941/942 2. interrupt requests (15) pin symbol i/o pin no. pin name description irq1 i 23 interrupt request 1 interrupt request pin interrupt receiving priority: irq15 is highest priority and irq1 is lowest. a choice of four interrupt waveforms is available by mode setting for each of the 15 pins independently, including h level, l level, rising edge, and falling edge. each input has a filtering function for short pulse signals, by which an interrupt request is recognized once a signal is detected at active level at three successive rising edges of the internal clock signal. once an interrupt request is detected, it passes through priority control and masking control and is output at the irl<3:0> pins as an interrupt request to the mpu. if these pins are not used, they should be fixed at inactive level. irq2 i 22 interrupt request 2 irq3 i 15 interrupt request 3 irq4 i 14 interrupt request 4 irq5 i 13 interrupt request 5 irq6 i 12 interrupt request 6 irq7 i 6 interrupt request 7 irq8 i 5 interrupt request 8 irq9 i 4 interrupt request 9 irq10 i 3 interrupt request 10 irq11 i 2 interrupt request 11 irq12 i 144 interrupt request 12 irq13 i 143 interrupt request 13 irq14 i 142 interrupt request 14 irq15 i 141 interrupt request 15
10 MB86941/942 3. timer signals (16) pin symbol i/o pin no. pin name description clk0 i 61 clk0 : timer clock 0 to clk3 : timer clock 3 timer control signal pin these pins are used to input an external clock signal to the timer. in external clock mode these signals are synchronized with the internal clock. in0 i 62 out0 o 65 clk1 i 71 in0 : timer input 0 to in3 : timer input 3 input pin for count operation control signals to the timer in mode0 through mode3, the input signal is a gate signal. in mode4, the pins input an external trigger signal. in1 i 70 out1 o 67 clk2 i 76 out0 : timer output 0 to out3 : timer output 3 timer output pin the output waveform is determined by the mode setting: ? periodic signal waveform output ? square wave output ? one-shot pulse waveform output at reset, an l level signal is output. in2 i 77 out2 o 79 clk3 i 74 in3 i 75 out3 o 80 ack0 i 63 asynchronous clock 0 prescaler asynchronous clock pin input can be asynchronous with respect to the system clock signal input at the clock pin. if an external clock signal is selected by the prs0 and prs1 registers, this signal can be used as a source clock for the prescaler. the clock signal divided by the prescaler is output at the prsck0, prsck1 pins. if these pins are not used, they should be fixed at l level. ack1 i 69 asynchronous clock 1 prsck0 o 64 prescaler clock output 0 prescaler clock output pin an l level signal is output at reset. prsck1 o 68 prescaler clock output 1
11 MB86941/942 4. sdtr signals (24) (continued) pin symbol i/o pin no. pin name description dsr0# i 26 data set ready 0 modem control signal dsr input pin the status of these pins is indicated at the status register bit 7. dsr1# i 60 data set ready 1 rts0# o 28 request to send 0 modem control signal rts output pin set the command register bit 5 to 1 to output an l signal, or to 0 to output an h signal. rts1# o 58 request to send 1 dtr0# o 31 data terminal ready 0 these pins can be used as a data terminal ready signal or a rate select signal of modem.set the command register bit 1 to 1 to output an l signal, or to 0 to output an h signal. dtr1# o 56 data terminal ready 1 cts0# i 27 clear to send 0 modem clear to send pin to enable sending, the command register bit 0 must be set to 1 and also an l level signal must be input at these pins. cts1# i 59 clear to send 1 trndt0 o 29 transmit data 0 transmit data pin parallel data written to the data register is converted to serial data and output from these pins. in asynchronous mode, a start bit and stop bit are attached, and a parity bit may be attached if necessary. if there is no data to be sent in the sdtr module, in synchronous mode a synchronizing character is output and in asynchronous mode the pins go to mark mode. if a send-prohibited setting (command register bit 0 set to 0) is in effect, or if an h signal is input at the cts# pin, these pins to mark mode. however if a send-prohibited setting is entered while a sending operation is in progress, all sending data already written will be sent before these pins go to mark mode. in addition, in bisynchronous mode if the first synchronization character is being sent (synchronization standby), then these pins will go to mark mode after sending the second synchronization character. trndt1 o 57 transmit data 1 temp0 o 42 transmit empty 0 these pins indicate whether sending data is present. if there is no data to be sent in the sdtr module, the signal level is h. as soon as one byte of sending data is written, these pins go to l level at the fall of the write signal. temp1 o 46 transmit empty 1 trdy0 o 33 transmit ready 0 transmit ready output pin when the cts# signal is l and the command register is set to enable sending, these pins send an h level signal whenever the sending data buffer is empty. trdy1 o 52 transmit ready 1
12 MB86941/942 (continued) pin symbol i/o pin no. pin name description tclk0# i 41 transmit clock 0 transmit clock input pin in synchronous mode, the sending bit rate is fixed at the sending clock 1, so that the clock signal input at these pins becomes the sending bit rate. in asynchronous mode, the sending bit rate will be the sending clock signal 1, or 1/16, or 1/64 depending on the bit rate setting in the mode register. for example, if a 19.2 khz clock signal is input at the tclk# pin, the sending bit rate will be 19200 pbs with an 1 setting, or 1200 pbs with an 1/16 setting, or 300 pbs with an 1/64 setting. sending data is output in synchronization with the falling edge of the sending clock signal. tclk1# i 48 transmit clock 1 rcvdt0 i 40 receive data 0 receive data input pin serial data input to these pins is converted to parallel data in the sdtr module and then can be read by the data bus. rcvdt1 i 50 receive data 1 rclk0 i 34 receive clock 0 receive clock input pin in synchronous mode, the receiving bit rate is fixed at the receiving clock 1, so that the clock signal input at these pins becomes the receiving bit rate. in asynchronous mode, the receiving bit rate will be the sending clock signal 1, or 1/16, or 1/64 depending on the bit rate setting in the mode register. for example, if a 19.2 khz clock signal is input at the rclk pin, the receiving bit rate will be 19200 pbs with an 1 setting, or 1200 pbs with an 1/16 setting, or 300pbs with an 1/64 setting. receiving data is sampled in synchronization with the rising edge of the receiving clock signal. note that in asynchronous mode 1 speed differs from 1/16 and 1/64 speeds in that external synchronization of the rclk and rcvdt signals is required. rclk1 i 51 receive clock 1
13 MB86941/942 (continued) pin symbol i/o pin no. pin name description sybrk0 i/o 32 synchronous/break detect 0 these pins can function as synchronization detect input, synchronization detect output, or break detect output pins, depending on the mode setting. ? external synchronization mode setting: synchronization signals are input at these pins. when the rclk is h level and these pins receive an h signal in hunting operation, the data sampled at the next rise of rclk is the starting bit of the receiving data. ? internal synchronization mode: these pins are used as the synchronization character detect output pins. when incoming data matches the synchronization character register setting (both characters must match in bisynchronous mode), an h signal is output here. next, the status register is read and this signal returns to l at the end of the read signal. ? asynchronous mode: these pins function as break detect output pins. immediately after a framing error, an h signal is output if all receiving data values (one frame including start bit, parity bit, and stop bit) are 0. this h signal is cancelled if a 1 data is received before a reset is applied. sybrk1 i/o 53 synchronous/break detect 1 rrdy0 o 43 receive ready 0 receive ready output pin these pins are h level, when serial data received at the rcvdt0, rcvdt1 pins is converted to parallel data in the sdtr module and is in readable form. then after the received data is read, these pins becomes l level at the end of the read signal. rrdy1 o 44 receive ready 1
14 MB86941/942 5. rcstg signals (11) pin symbol i/o pin no. pin name description cs0# o 16 expansion chip select 0 expansion chip select output pin when the input to the rcs# pin is l, one of these chip select signals will be active depending on the combination of input signals to the a0, a1 pins. cs1# o 21 expansion chip select 1 cs2# o 24 expansion chip select 2 cs3# o 25 expansion chip select 3 re# o 35 expansion read enable expansion read enable output pin when the input to the rcs# pin is l and a bus cycle begins with an h input to the rd/wr# pin, this pin produces a pulse of the designated width and the designated timing. we# o 36 expansion write enable expansion write enable output pin when the input to the rcs# pin is l and a bus cycle begins with an l input to the rd/wr# pin, this pin produces a pulse of the designated width and the designated timing. ds# o 47 expansion data strobe expansion data strobe output pin when a bus cycle begins with the rcs# pin input at l level, this pin produces a pulse of the designated width and the designated timing. rcs# i 37 resource chip select resource chip select pin. this pin is used to input the chip select signal supplied to the module rcstg. when the module rcstg is used to generate the external resource chip select signals cs0# to cs3#, read strobe re#, write strobe we#, and data strobe ds#, the corresponding areas must be decoded. this pin has internal pull-up resistance (MB86941 only). a0 i 38 address 0 these are the input pins for the address signal to the module rcstg. when the module rcstg is used to generate the external resource chip select signals cs0# to cs3#, read strobe signal re#, write strobe signal we#, and data strobe signal ds#, this address input signal is used to designate the byte position in the corresponding area. when the input to the rcs# pins is l level, the input signal to these pins determines which of the external resource chip select signals cs0# to cs3# goes active. these pins have internal pull-up resistance (MB86941 only). a1 i 39 address 1 rdyout# o 49 ready out this is the output pin for the ready signal generated by the module rcstg. when the module rcstg is used to generate the external resource chip select signals cs0#-cs3#, read strobe signal re#, write strobe signal we#, and data strobe signal ds#, the ready signal is output from these pins to the mpu. when any of the signals cs0# to cs1# is at l level, this signal is asserted with the designated timing interval.
15 MB86941/942 6. i/o port signals (16) 7. sio signals (4) pin symbol i/o pin no. pin name description ipd0 i/o 72 i/o port 0 signal i/o port these pins may be used for input or output, as determined by register setting. these pins have internal pull-up resistance (MB86941 only). ipd1 i/o 78 i/o port 1 ipd2 i/o 84 i/o port 2 ipd3 i/o 85 i/o port 3 ipd4 i/o 86 i/o port 4 ipd5 i/o 87 i/o port 5 ipd6 i/o 94 i/o port 6 ipd7 i/o 95 i/o port 7 ipd8 i/o 96 i/o port 8 ipd9 i/o 98 i/o port 9 ipd10 i/o 99 i/o port 10 ipd11 i/o 103 i/o port 11 ipd12 i/o 104 i/o port 12 ipd13 i/o 105 i/o port 13 ipd14 i/o 106 i/o port 14 ipd15 i/o 107 i/o port 15 pin symbol i/o pin no. pin name description siclk i/o 114 sio clock this is the input/output pin for the clock signal used for sio serial data transfer. in external clock mode, the clock signal for serial data transfer is input at this pin. in internal clock mode, the clock signal from the internal clock generator is output at this pin. this pin has internal pull-up resistance (MB86941 only). sirxd i 109 sio receive data sio receive data input pin this pin receives data input lsb first, synchronously with the siclk pin clock signal. this pin has internal pull-up resistance (MB86941 only). sitxd o 110 sio transmit data sio transmit data output pin this pin outputs data lsb first, synchronously with the siclk pin clock signal. siirq o 111 sio interrupt request sio interrupt request output pin
16 MB86941/942 8. v dd , v ss , n.c. (24/25) * : no.17 is a ready2# pin for MB86941. pin symbol i/o pin no. pin name description v dd ? 1, 18, 54, 73, 90, 126 ? power supply input pin v ss ? 9, 19, 30, 45, 55, 66, 81, 91, 102, 117, 127, 138 ? grand pin n.c. ? 97, 108, 112, 115, 116, 123 (17*) ? these pins shall be used as an open pin. no. 17 is also an open pin for mb86942.
17 MB86941/942 n absolute maximum ratings *1: v ss = 0 v *2: at 1 pin for 1 second *3: output pins other than d < 15 : 0 >, ready1# and redy2# *4: d < 15 : 0 > *5: ready1#, ready2# warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit MB86941 mb86942 power supply voltage v dd C0.5 to +0.6* 1 C0.5 to +4.0* 1 v input voltage v i C0.5 to v dd + 0.5* 1 v output voltage v o C0.3 to v dd + 0.5* 1 C0.5 to v dd + 0.5* 1 v storage temperature t stg C40 to 125 c output current* 2 i o at maximum v dd *3 v o = v dd +40 v o = v dd +60 ma v o = 0 C40 *4 v o = v dd +80 v o = 0 C40 v o = 0 C60 *5 v o = v dd +120 v o = 0 C80 parameter symbol value unit MB86941 mb86942 power supply voltage v dd 4.75 to 5.25 3.15 to 3.45 v operating temperature t a 0 to +70 c
18 MB86941/942 n electric characteristics 1. dc characteristics (1) input characteristics (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) (2) output characteristics (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) *1: MB86941 ready1#, ready2# *2: MB86941 d < 15 : 0 > *3: MB86941 other than ready1#, ready2# and d < 15 : 0 > *4: mb86942 (3) power supply current (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) parameter symbol condition MB86941 mb86942 unit min. max. min. max. h level input voltage v ih clock 2.8 v dd v dd 0.65 v dd + 0.15 v irq15 to irq1 2.4 v dd other 2.2 v dd l level input voltage v il irq15 to irq1 v ss 0.6 v ss v dd 0.25 v other v ss 0.8 parameter symbol condition MB86941 mb86942 unit min. max. min. max. h level output voltage v oh i oh = C8 ma* 2 4.0 v dd v i oh = C3.2 ma* 3 i oh = C4 ma* 4 v dd C 0.5 v dd l level output voltage v ol i ol = +12 ma* 1 v ss 0.4 v i ol = +8 ma* 2 i ol = +3.2 ma* 3 i ol = +4 ma* 4 v ss 0.4 parameter symbol condition MB86941 mb86942 unit min. max. min. max. power supply current i cc 230 190 ma
19 MB86941/942 2. capacitances (v dd = v i = 0 v, f = 1 mhz, t a = +25 c) 3. ac test conditions (1) input/output signal waveform parameter symbol value unit min. max. input capacitance c in 16pf output capacitance c out 16pf i/o capacitance c i / o 16pf t r MB86941: 1.5 v 10% t f 90% mb86942: 1 / 2 (v ih + v il ) MB86941 : 1.5 v mb86942: v dd / 2 MB86941: 1.5 v mb86942: v dd / 2 MB86941: 1.5 v mb86942: v dd / 2 MB86941: 1.5 v mb86942: v dd / 2 MB86941: 1.5 v mb86942: 1 / 2 (v ih + v il ) t phl t pzl t pzh t plh t plz t phz 0.5 v 0.5 v v ih v il v oh v ol v ol v oh t r , t f < 5 ns MB86941: v ih = clock 2.8v, irq15 to irq1 2.4 v, other 2.2 v, v il = 0.4 v mb86942: v ih = v dd 0.65, v il = v dd 0.25 input signal waveform output delay output enable/ disable
20 MB86941/942 (2) load circuit 4. ac characteristics (1) reset signal (hardware reset) (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) t clk : see (2) clock signals. condition load capacitance MB86941 mb86942 normal output 60 pf 30 pf tri-state output (ready1#, ready2#) 65 pf bi-directional pin (d bus) 85 pf 30 pf signal transmit sw1 sw2 l ? h, h ? loffoff l ? z, z ? lonoff l ? z, z ? loffon parameter symbol value unit min. max. reset pulse width t rstw 20 t clk MB86941/2 v dd v ss output c r1 = 2 k w r2 = 2 k w sw1 sw2 lsi tester t rstw reset#
21 MB86941/942 (2) clock signal (clock) (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) (3) mpu interface (register read/write) (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) * : ready2# is available for MB86941. parameter symbol MB86941 mb86942 unit min. max. min. max. clock cycle time t clk 25 20 ns clock h pulse width t clkh 98ns clock l pulse width t clkl 98ns clock rise time t clkr 42ns clock fall time t clkf 42ns parameter symbol MB86941 mb86942 unit wsel = h wsel = l min. max. min. max. min. max. as# setup time t ass 11 7 7 ns as# hold time t ash 002 ns cs# setup time t css 857 ns cs# hold time t csh 002 ns rd/wr# setup time t rws 13 9 7 ns rd/wr# hold time t rwh 002 ns rs < 5 : 0 > setup time t rss 857 ns rs < 5 : 0 > hold time t rsh 002 ns ready1#, ready2# output delay time t rdyf 018018018 ns ready1#, ready2# hold time t rdyh 520520520 ns d < 15 : 0 > output delay time at reading t odd 021023023 ns d < 15 : 0 > output hold time at reading t odh 525525520 ns d < 15 : 0 > input setup time at writing t ids 11 7 7 ns d < 15 : 0 > input hold time at writing t idh 000 ns t clkh t clkf t clkl t clkr t clk clock
22 MB86941/942 clock ? wsel = h as# cs# rd/wr# rs < 5 : 0 > ready1# ready2#* d < 15 : 0 > at read d < 15 : 0 > at write t ash t ass t csh t rwh t rsh t ids t ash t css t rws t rss t rdyf t odd t csh t rwh t rsh t rdyh t odh t idh high-z high-z high-z high-z mb86942: h level output mb86942: h level output * : only for MB86941.
23 MB86941/942 clock ? wsel = l as# cs# rd/wr# rs < 5 : 0 > ready1# ready2#* d < 15 : 0 > at read d < 15 : 0 > at write t ash t ass t csh t rwh t rsh t ids t ash t css t rws t rss t rdyf t odd t csh t rwh t rsh t rdyh t odh t idh high-z high-z high-z mb86942: h level output * : only for MB86941. mb86942: h level output
24 MB86941/942 (4) interrupt signal ? interrupt input pulse width (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) t clk : see (2) clock signals. *1: when the trigger mode is set for h level signal input or rise-edge, a pulse of at least this width is received as a req-ff signal. note that this rule does not guarantee that no interrupts less than this width will be received. *2: when the trigger mode is set for l level signal input or fall-edge, a pulse of at least this width is received as a req-ff signal. note that this rule does not guarantee that no interrupts less than this width will be received. parameter symbol value unit min. max. irq input h level pulse width* 1 t ihw 6 t clk + 10 ns irq input l level pulse width* 2 t ilw 6 t clk + 10 ns t ihw t ilw irqx
25 MB86941/942 ? interrupt input clear (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) t clk : see (2) clock signals. * : this parameter means the condition of request clear execution and is applied at level trigger modes. parameter symbol value unit min. max. irqx clear setup time* t irqs 2 t clk + 10 ns t irqs irqx irqx (high level trigger) clock (low level trigger) as# rd/wr# req clear
26 MB86941/942 ? interrupt level output (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) parameter symbol value unit min. max. irl < 3 : 0 > clear delay time t irlcd 80ns irl < 3 : 0 > mask delay time t irlmd 80ns clock as# cs# rd/wr# rs < 5 : 0 > ready1# ready2#* irs < 3 : 0 > t irlmd , t irlcd high-z irl clear irl mask high-z * : only for MB86941. mb86942: h level output mb86942: h level output
27 MB86941/942 (5) prescaler timer ? prescaler input (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) * : applied in prescaler external clock mode. when the prescaler output is used as a timer signal, the timer input clock requirements must be met. ? prescaler output (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) *1: applied when the prescaler register select field is set to 0. n: value set in the prescaler register prescale value field *2: applied when the prescaler register select field is set to any value other than 0. m: value set in the prescaler register select field. n: value set in the prescaler register prescale value field. *3: when the prescaler register select field is set to 0, the prsckx output is fixed at l level. *4: t pck has the following prescaler input clock period. internal clock mode: t pck = 2 t clk (for t clk , see (2) clock signals) external clock mode: t pck = t ack (for t ack , see (5) prescaler timer unit/prescaler input) parameter symbol MB86941 mb86942 unit min. max. min. max. prescaler input clock cycle time* t ack 50 40 ns prescaler input clock h level width* t achw 22 15 ns prescaler input clock l level width* t aclw 22 15 ns prescaler input clock rise time* t acr 55ns prescaler input clock fall time* t acf 55ns parameter symbol standard value unit prescaler output l level width* 1, * 3 t psclw 1 t pck * 4 prescaler output h level width* 1, * 3 t pschw n C 1 t pck * 4 prescaler output l level width* 2, * 3 t psclw n 2 m C 1 t pck * 4 prescaler output h level width* 2, * 3 t pschw n 2 m C 1 t pck * 4 t achw t acr aclk0, aclk1 t ack t aclw t acf prsck0, prsck1 t psclw t pschw
28 MB86941/942 ? timer (at external clock mode) (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) t clk : see (2) clock signals. ? timer output 1 (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) parameter symbol value unit min. max. timer input clock h level width t tckh 3t clk timer input clock l level width t tckl 3t clk gate signal (in pin) setup time (for clkx) t gs 10 ns gate signal (in pin) hold time (for clkx) t gh 0ns parameter symbol value unit min. max. out output delay time (for clock) t outd1 30ns t tckh clkx t gs inx (as in pin of event set l ) inx (as in pin of event set h ) t tckl t gh t outd1 clock outx
29 MB86941/942 ? timer output 2 (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) t clk : see (2) clock signals. * : applied to the following cases. ? setting mode (write to tcr). ? after setting to mode0, write to reload register/read count register. ? after setting to mode1, write to reload register/read count register. ? after setting to mode3, write to reload register. parameter symbol value unit min. max. out output delay time* t outd2 3 t clk + 30 ns clock as# cs# rd/wr# rs < 5 : 0 > ready1# ready2#* outx t outd2 high-z set to mode, read count * : only for MB86941. mb86942: h level output mb86942: h level output high-z
30 MB86941/942 (6) sdtr ? dsr#, rrdy (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) t clk : see (2) clock signals. parameter symbol value unit min. max. dsr# setup time for resistor read t dsrs 28 t clk interval from register read to rrdy off t rrdyl 0 100 ns clock as# cs# rd/wr# d < 15 : 0 > ready1# ready2#* dsr# t dsrs t rrdyl high-z register read high-z rs < 5 : 0 > rrdy * : only for MB86941. mb86942: h level output mb86942: h level output
31 MB86941/942 ? dtr#, rts#, trdy (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) t clk : see (2) clock signals. parameter symbol value unit min. max. delay time from register write to dtr# output t dtrod 040t clk delay time from register write to rts# output t rtsod 040t clk delay time from register write to trdy output t trdyod 0 100 ns clock as# cs# rd/wr# d < 15 : 0 > ready1# ready2#* dsr#, rts# t trdyod t rrdyl , t dtrod high-z register write rs < 5 : 0 > trdy mb86942: h level output mb86942: h level output high-z * : only for MB86941.
32 MB86941/942 ? command write cycle (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) t clk : see (2) clock signals. parameter symbol value unit min. max. command write cycle time (for initial value setup) t cmdc 14 t clk command write cycle time (for asynchronous mode) t cmdc 20 t clk command write cycle time (for synchronous mode) t cmdc 40 t clk clock as# cs# rd/wr# ready1# ready2#* t cmdc * : only for MB86941.
33 MB86941/942 ? transmit clock and transmit data (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) t clk : see (2) clock signals. parameter symbol syncroh mode, 1 mode 1/16, 1/64 mode unit min. max. min. max. transmit clock h width t tckhw 32 4 t clk transmit clock l width t tcklw 14 4 t clk interval from transmit clock falling to transmit data output t tckdt 0 100 0 100 ns tclk# ( 1/64 mode) trndt t tckdt tclk# ( 1/64 mode) tclk# ( 1 mode, sync mode) t tcklw t tckhw t tcklw t tckhw t tckdt 64 1 2 3 3031 32333435 6263 641 2 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2
34 MB86941/942 ? receive clock and receive data (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) t clk : see (2) clock signals. parameter symbol syncroh mode, 1 mode 1/16, 1/64 mode unit min. max. min. max. receive clock period t rck 62 8 t clk receive clock h width t rckhw 12 4 t clk receive clock l width t rcklw 74t clk receive data setup time t rds 66t clk receive data hold time t rdh 66t clk rclk ( 1 mode, sync mode) t tckdt rcvdt t rcklw t rckhw t rds t rdh t rcklw 64 1 2 3 303132333435 62636412 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 rclk ( 1/16 mode) rclk ( 1/64 mode) t rck 2 t rck
35 MB86941/942 ? sybrk signal timing for external synchronous mode (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) t clk : see (2) clock signals. ? transmit and receive control signal timing (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) t clk : see (2) clock signals. parameter symbol value unit min. max. sybrk setup time (for rclk) t brks 0t clk sybrk hold time (for rclk) t brkh 10 t clk parameter symbol value unit min. max. delay time from tclk# rising (last bit) to trdy rising t tckrdy 36t clk delay time from tclk# rising (last bit) to temp rising t tckemp 24t clk delay time from rclk rising (last bit) to rrdy rising t rckrdy 35t clk detection time from rclk rising (last bit) to internal sync (sybrk pin) t sycd1 62t clk detection time rclk rising (last bit) to internal sync (status data buffer register) t sycd2 70t clk t brkh rclk sybrk t brks
36 MB86941/942 ? receive timing example 1 (asynchronous mode, 5 data bits, parity enable, 2 stop bits) rs < 5 : 0 > rcvdt rrdy oerr bit ferr bit sybrk write strobe (internal signal) read strobe (internal signal) < 1 >: control data buffer selection < 2 >: status data buffer selection < 1 > < 2 > < 1 > < 2 > < 1 > d 0 d 1 d 2 d 3 d 4 ps 1 s 2 d 0 d 1 d 2 d 3 d 4 ps 1 s 2 d 0 d 1 d 2 d 3 d 4 ps 1 s 2 d 0 d 1 d 2 d 3 d 4 ps 1 s 2 data 1 data 2 rcven set error reset error reset data 2 t rckrdy data 1 loss framing error break pattern detection
37 MB86941/942 ...... ...... ...... ...... ...... ...... ...... ? transmit timing example 1 (asynchronous mode, 6 data bits, parity enable, 2 stop bits) < 1 >: transmit data buffer selection < 2 >: control data buffer selection d 0 d 1 d 2 d 3 d 4 d 5 s 1 s 2 < 1 > < 1 > < 1 > < 2 > < 2 > < 1 > d 0 d 1 d 2 d 3 d 4 d 5 s 1 s 2 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 4 d 5 s 1 s 2 data 1 data 2 data 3 data 4 data 1 data 2 data 3 data 4 break set break clear t tckrdy t tckemp rs < 5 : 0 > trndt trdy bit trdy temp cts# write strobe (internal signal)
38 MB86941/942 ...... ...... ...... ...... ...... ...... ...... ? transmit timing example 2 (synchronous mode, bisynchronous mode, 5 data bits, parity enable ) rs < 5 : 0 > trndt < 1 >: transmit data buffer selection < 2 >: control data buffer selection d 0 d 1 d 2 d 3 d 4 p < 1 > trdy bit trdy temp cts# < 1 > < 2 > < 2 > < 1 > < 1 > data 1 data 2 data 3 data 4 data 1 data 2 data 3 data 4 break set break clear d 0 d 1 d 2 d 3 d 4 pd 0 d 1 d 2 d 3 d 4 pd 0 d 1 d 2 d 3 d 4 pd 0 d 1 d 2 d 3 d 4 pd 0 d 1 d 2 d 3 d 4 synchronous character 1 synchronous character 2 write strobe (internal signal)
39 MB86941/942 ? transmit timing example 2 (synchronous mode, bisynchronous mode, 5 data bits, parity enable ) rs < 5 : 0 > rcvdt sybrk d 0 d 1 d 2 d 3 p d 4 d 0 d 1 d 2 d 3 p d 4 d 0 d 1 d 2 d 3 p d 4 p d 4 d 0 d 1 d 2 d 3 d 4 d 0 d 1 d 2 d 3 d 4 pd 0 d 1 d 2 d 3 d 4 p d 0 d 1 d 2 d 3 p rrdy sybrk bit oerr bit t sycd1 t sycd2 < 2 > < 2 > < 2 > < 1 > < 1 > < 3 > < 3 > < 2> : recieve data buffer selection <1> : control data buffer selection <3> : status data buffer selection synchronous character 1 synchronous character 2 data 1 data 1 data 2 data 3 data 3 synchronous character 1 status error reset synchronous character 1 synchronous character 2 status data 2 loss emh, rcven set write strobe (internal signal) read strobe (internal signal)
40 MB86941/942 (7) rcstg ? control signal output timing (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) parameter symbol MB86941 mb86942 unit min. max. min. max. rcs# setup time t rcss 57ns rcs# hold time t rcsh 52ns a < 1 : 0 > setup time t ads 57ns a < 1 : 0 > hold time t adh 52ns delay time from rcs#, a1, a0 fix to cs3# to cs0# fix t ecsd 1518ns delay time from clock to re#, we#, ds# fix t ecntd 1518ns
41 MB86941/942 clock as# rcs# rd/wr# *1: set register rtr0, rtr1. *2: set register wtr0, wtr1. ? register read control signal output timing a < 1 : 0 > cs3# to cs0# ds# re# we# rdyout# rd/wr# ds# re# we# rdyout# t ecntd t ecntd t ecsd t adh t rcsh t ecsd t rcss t ads t ecntd t ecntd t ecntd t ecntd t ecntd t ecntd *1 *1 *1 *1 *2 *2 *2 *2 h h
42 MB86941/942 (8) sio ? control signal output timing (MB86941: v dd = 5 v 5%, t a = 0 to +70 c) (mb86942: v dd = 3.3 v 0.15 v, t a = 0 to +70 c) parameter symbol value unit min. max. siclk rise time t sclkr 3ns siclk fall time t sclkf 3ns setup time from siclk rise/fall to valid sirxd at receiving t srd 80 ns delay time from siclk rise/fall to sitxd output at transmitting t dtd 30ns hold time from siclk rise/fall to valid sitxd t htd 80 ns siclk sirxd t srd t dtd siclk siclk sitxd t htd t sclkr t sclkf
43 MB86941/942 n notes on use when the prescaler is used in external clock mode, and the prescaler output signal is used as the timer operating clock, use the following settings. when the prescaler and timer are set to the following modes, the timer output signal out will not change at the anticipated time: prescaler: external clock mode (prescaler register bit15 = 1). timer: prescaler internal output signal used as operating clock, without using the external input pin (tcr bit 10, 9 = 10). set the timer operating clock to external clock (tcr bits 10, 9 = 01), and connect the prescaler output pin prsck externally to the timer external clock input pin clk.
44 MB86941/942 n register map (continued) block name rs5 to rs0 (hex) register name bit 1514131211109876543210 irc 00 h tm0 (trigger mode 0) ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 01 h tm1 (trigger mode 1) ch7 ch6 ch5 ch4 ch3 ch2 ch1 02 h rs (req sense) 151413121110987654321 03 h rc (req clear) 151413121110987654321 04 h mask (mask) 151413121110987654321im 05 h irl (irl latch/clear) cl irl latch reserved 06 h reserved 07 h sdtr 0 08 h sdr0 (sdtr data 0) transmit data/ receive data 09 h scsr0 (sdtr cm/st 0) control data/status data reserved 0a h reserved 0b h sdtr 1 0c h sdr1 (sdtr dsta 1) transmit data/ receive data 0d h scsr1 (sdtr cm/st 1) control data/ status data reserved 0e h reserved 0f h prescaler0 10 h prs0 (prescale 0) ex test select prescale value
45 MB86941/942 (continued) block name rs5 to rs0 (hex) register name bit 1514131211109876543210 timer 0 11 h tcr0 (timer control 0) ot in test ce cs ocont iv mode event 12 h rvr0 (reload value 0) reload value 13 h cvr0 (count value 0) count value prescaler1 14 h prs1 (prescale 1) ex test select prescale value timer 1 15 h tcr1 (timer control 1) ot in test ce cs ocont iv mode event 16 h rvr1 (reload value 1) reload value 17 h cvr1 (count value 1) count value reserved 18 h reserved timer 2 19 h tcr2 (timer control 2) ot in test ce cs ocont iv mode event 1a h rvr2 (reload value 2) reload value 1b h cvr2 (count value 2) count value reserved 1c h reserved timer 3 1d h tcr3 (timer control 3) to in test ce cs ocont iv mode event 1e h rvr3 (reload value 3) reload value 1f h cvr3 (count value 3) count value
46 MB86941/942 (continued) block name rs5 to rs0 (hex) register name bit 1514131211109876543210 i/o port 20 h pdr (port data) port data 21 h dcr (port direction) port direction reserved 22 h reserved 23 h sio 24 h scr (serial control) control 25 h str (serial status) status 26 h rdr (receive data) receive data 27 h tdr (transmit data) transmit data 28 h trr (transfer rate) rate select reserved 29 h reserved 2a h 2b h timing0 2c h rtr0 (read timing 0) trew trdsw trel trdsl 2d h wtr0 (write timing 0) twew twdsw tweltwdsl timing1 2e h rtr1 (read timing 1) trew trdsw trel trdsl 2f h wtr1 (write timing 1) twew twdsw tweltwdsl
47 MB86941/942 n ordering information part number package remarks MB86941pfv 144-pin plastic qfp (fpt-144p-m03) mb86942pfv 144-pin plastic qfp (fpt-144p-m03)
48 MB86941/942 n package dimension c 1995 fujitsu limited f144003s-2c-3 details of "a" part details of "b" part 0.500.20(.020.008) 0 10? 0.40(.016)max 0.15(.006)max 0.15(.006) 0.15(.006) 22.600.20(.890.008)sq 20.000.10(.787.004)sq 0.200.10 (.008.004) 0.08(.003) m 0.1250.05 (.005.002) 3.85(.152)max 0.05(.002)min (stand off) 21.60 17.50 (.850) nom (.689) ref 0.10(.004) "a" "b" 36 37 72 73 108 109 144 1 index 0.50(.0197)typ lead no. (mounting height) dimensions in mm (inches) 144-pin plastic qfp (fpt-144p-m03)
49 MB86941/942 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9812 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

▲Up To Search▲

Price & Availability of MB86941

	To Download MB86941 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .